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ltc6915 1 6915fb typical application features description zero drift, precision instrumentation amplifier with digitally programmable gain the ltc ? 6915 is a precision programmable gain instru - mentation amplifier. the gain can be programmed to 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, or 4096 through a parallel or serial interface. the cmrr is typi - cally 125db with a single 5v supply with any programmed gain. the offset is below 10v with a temperature drift of less than 50nv/c. the ltc6915 uses charge balanced sampled data tech - niques to convert a differential input voltage into a single ended signal that is in turn amplified by a zero-drift op - erational amplifier. the differential inputs operate from rail-to-rail and the single-ended output swings from rail-to-rail. the ltc6915 can be used in single power supply applications as low as 2.7v, or with dual 5v supplies. the ltc6915 is available in a 16-lead ssop package and a 12-lead dfn surface mount package. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners differential bridge amplifier with gain programmed through the serial interface applications n 14 levels of programmable gain n 125db cmrr independent of gain n gain accuracy 0.1% (typ) n maximum offset voltage of 10v n maximum offset voltage drift: 50nv/c n rail-to-rail input and output n parallel or serial (spi) interface for gain setting n supply operation: 2.7v to 5.5v n typical noise: 2.5v p-p (0.01hz to 10hz) n 16-lead ssop and 12-lead dfn packages n thermocouple amplifiers n electronic scales n medical instrumentation n strain gauge amplifier n high resolution data acquisition ? + 3v resistor array mux 4-bit latch q0 q1 q2 q3 q4 q5 q6 q7 8-bit shift-register hold_thru p to other devices cs(d0)d in (d1) clk(d2)d out (d3) parallel_serial in + in _ 32 11 67 8 9 r < 10k c s c h ltc6915 ssop package 0.1f v + v ? shdn dgnd 135 1610 14 out ref 15 14 c f 6915 ta01 sense 3v downloaded from: http:///
ltc6915 2 6915fb absolute maximum ratings total supply voltage (v + to v ? ) ................................. 11v input current ........................................................ 10ma |v in + ? v ref | ........................................................ 5.5v |v in ? ? v ref | ........................................................ 5.5v |v + ? v dgnd | ........................................................ 5.5v |v dgnd ? v ? | ........................................................ 5.5v digital input voltage ........................................... v ? to v + operating temperature range ltc6915c .............................................. ?0c to 70c ltc6915i ............................................. ?40c to 85c ltc6915h .......................................... ?40c to 125c junction temperature (gn package) .................................................... 150c (dfn package) .................................................. 125c storage temperature (gn package) ..................................... ?65c to 150c (dfn package) ................................... ?65c to 125c lead temperature (soldering 10 sec) .................... 300c (note 1) 1211 10 98 7 13 v ? 12 3 4 5 6 v + outref parallel_serial dgnd d out (d3) in ? in + v ? cs(d0) d in (d1) clk(d2) top view de12 package 12-lead (4mm 3mm) plastic dfn t jmax = 125c, ja = 160c/w exposed pad (pin 13) is v ? , must be soldered to pcb top view gn package 16-lead narrow plastic ssop 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 shdn in ? in + v ? hold_thru cs(d0) d in (d1) clk(d2) v + outsense ref nc parallel_serial dgnd d out (d3) t jmax = 150c, ja = 135c/w pin configuration order information lead free finish tape and reel part marking package description temperature range ltc6915cde#pbf ltc6915cde#trpbf 6915 12-lead (4mm 3mm) plastic dfn 0c to 70c ltc6915ide#pbf ltc6915ide#trpbf 6915i 12-lead (4mm 3mm) plastic dfn ?40c to 85c ltc6915cgn#pbf ltc6915cgn#trpbf 6915 16-lead narrow plastic ssop 0c to 70c ltc6915ign#pbf ltc6915ign#trpbf 6915i 16-lead narrow plastic ssop ?40c to 85c ltc6915hgn#pbf ltc6915hgn#trpbf 6915h 16-lead narrow plastic ssop ?40c to 125c lead based finish tape and reel part marking* package description temperature range ltc6915cde ltc6915cde#tr 6915 12-lead (4mm 3mm) plastic dfn 0c to 70c ltc6915ide ltc6915ide#tr 6915i 12-lead (4mm 3mm) plastic dfn ?40c to 85c ltc6915cgn ltc6915cgn#tr 6915 16-lead narrow plastic ssop 0c to 70c ltc6915ign ltc6915ign#tr 6915i 16-lead narrow plastic ssop ?40c to 85c ltc6915hgn ltc6915hgn#tr 6915h 16-lead narrow plastic ssop ?40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc6915 3 6915fb electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. symbol parameter conditions min typ max units v + = 3v, v ? = 0v, v ref = 200mv gain error (note 2) a v = 1 (r l =10k) l ?0.075 0 0.075 % gain error (note 2) a v = 2 to 32 (r l = 10k) l ?0.5 0 0.5 % gain error (note 2) a v = 64 to 1024 (r l = 10k) l ?0.6 ?0.1 0.6 % gain error (note 2) a v = 2048, 4096 (r l = 10k) l ?1 ?0.2 1.0 % gain nonlinearity a v = 1 l 3 15 ppm v os input offset voltage (note 3) v cm = 200mv ?3 10 v average input offset drift (note 3) t a = ?40c to 85c t a = 85c to 125c l l 50 100 nv/c nv/c i b average input bias current (note 4) v cm = 1.2v l 5 10 na i os average input offset current (note 4) v cm = 1.2v l 1.5 3 na en input noise voltage dc to 10hz 2.5 v p-p v + = 3v, v ? = 0v, v ref = 200mv cmrr common mode rejection ratio a v = 1024, v cm = 0v to 3v, ltc6915c a v = 1024, v cm = 0.1v to 2.9v, ltc6915i a v = 1024, v cm = 0v to 3v, ltc6915i a v = 1024, v cm = 0.1v to 2.9v, ltc6915h a v = 1024, v cm = 0v to 2.97v, ltc6915h l l l l l 100 100 95 100 85 119 119 119 db db db db db psrr power supply rejection ratio (note 5) v s = 2.7v to 6v l 110 116 db output voltage swing high (referenced to v ? ) sourcing 200a sourcing 2ma l l 2.95 2.75 2.98 2.87 v v output voltage swing low (referenced to v ? ) sinking 200a sinking 2ma l l 18 130 50 300 mv mv supply current, parallel mode no load at out, v cm = 200mv l 0.88 1.3 ma supply current, serial mode (note 6) no load at out, capacitive load at d out (c l ) = 15pf, continuous clk frequency = 4mhz, cs = low, gain control code = 0001 l 1.1 1.65 ma supply current shutdown v shdn = 2.7v (hardware shutdown) v shdn = 1v, gain control code = 0000 (software shutdown) l l 1 125 4 180 a a shdn input high l 2.7 v shdn input low l 1 v shdn and hold_thru input current (note 2) l 5 a internal op amp gain bandwidth 200 khz slew rate 0.2 v/s internal sampling frequency 3 khz v + = 5v, v ? = 0v, v ref = 200mv gain error (note 2) a v = 1 (r l = 10k) l ?0.075 0 0.075 % gain error (note 2) a v = 2 to 32 (r l = 10k) l ?0.5 0 0.5 % gain error (note 2) a v = 64 to 1024 (r l = 10k) l ?0.6 ?0.1 0.6 % gain error (note 2) a v = 2048, 4096 (r l = 10k) l ?1 ?0.2 1 % gain nonlinearity a v = 1 l 3 15 ppm downloaded from: http:///
ltc6915 4 6915fb electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v os input offset voltage (note 3) v cm = 200mv ?3 10 v average input offset drift (note 3) t a = ?40c to 85c t a = 85c to 125c l 50 100 nv/c nv/c average input bias current (note 4) v cm = 1.2v l 5 10 na i os average input offset current (note 4) v cm = 1.2v l 1.5 3 na cmrr common mode rejection ratio a v = 1024, v cm = 0v to 5v, ltc6915c a v = 1024, v cm = 0.1v to 4.9v, ltc6915i a v = 1024, v cm = 0v to 5v, ltc6915i a v = 1024, v cm = 0.1v to 4.9v, ltc6915h a v = 1024, v cm = 0v to 4.97v, ltc6915h l l l l l 105 105 95 100 85 125 125 125 db db db db db psrr power supply rejection ratio (note 5) v s = 2.7v to 6v l 110 116 db output voltage swing high sourcing 200a sourcing 2ma l l 4.95 4.80 4.99 4.93 v v output voltage swing low sinking 200a sinking 2ma l l 17 120 50 300 mv mv v + = 5v, v ? = 0v, v ref = 200mv supply current, parallel mode no load at out, v cm = 200mv l 0.95 1.48 ma supply current, serial mode (note 6) no load at out, capacitive load at d out (c l ) = 15pf, continuous clk frequency = 4mhz, cs = low, gain control code = 0001 l 1.4 2 ma supply current, shutdown v shdn = 4.5v (hardware shutdown) v shdn = 1v, gain control code = 0000 (software shutdown) l l 2 135 10 200 a a shdn input high l 4.5 v shdn input low l 1 v shdn and hold_thru input current (note 2) l 5 a internal op amp gain bandwidth 200 khz slew rate 0.2 v/s internal sampling frequency 3 khz v + = 5v, v ? = ?5v, v ref = 0v gain error (note 2) a v = 1 (r l = 10k) l ?0.075 0 0.075 % gain error (note 2) a v = 2 to 32 (r l = 10k) l ?0.5 0 0.5 % gain error (note 2) a v = 64 to 1024 (r l = 10k) l ?0.6 ?0.1 0.6 % gain error (note 2) a v = 2048, 4096 (r l = 10k) l ?1 ?0.2 1 % gain nonlinearity a v = 1 l 3 15 ppm v os input offset voltage (note 3) v cm = 0mv 5 20 v average input offset drift (note 3) t a = ?40c to 85c t a = 85c to 125c l l 50 100 nv/c nv/c i os average input bias current (note 4) v cm = 1v l 4 10 na average input offset current (note 4) v cm = 1v l 1.5 3 na downloaded from: http:///
ltc6915 5 6915fb electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. cmrr common mode rejection ratio a v = 1024, v cm = ?5v to 5v, ltc6915c a v = 1024, v cm = ?4.9v to 4.9v, ltc6915i a v = 1024, v cm = ?5v to 5v, ltc6915i a v = 1024, v cm = ?4.9v to 4.9v, ltc6915h a v = 1024, v cm = ?5v to 4.97v, ltc6915h l l l l l 105 105 100 100 90 123 123 123 db db db db db psrr power supply rejection ratio (note 5) v s = 2.7v to 11v l 110 116 db output voltage swing high sourcing 200a sourcing 2ma l l 4.97 4.90 4.99 4.96 v v output voltage swing low sinking 200a sinking 2ma l l ?4.98 ?4.90 ?4.92 ?4.70 v v supply current, parallel mode no load, v cm = 0mv l 1.1 1.6 ma supply current, serial mode (note 6) no load at out, capacitive load at d out (c l ) = 15pf, continuous clk frequency = 4mhz, cs = low, gain control code = 0001 l 1.73 2.48 ma supply current, shutdown v shdn = 4v (hardware shutdown) v shdn = 1v, gain control code = 0000 (software shutdown) l l 160 25 240 a a shdn input high l 4 v shdn input low l 1 v v + = 5v, v ? = ?5v, v ref = 0v shdn and hold_thru input current (note 2) l 5 a internal op amp gain bandwidth 200 khz slew rate 0.2 v/s internal sampling frequency 3 khz digital i/o, all digital i/o voltage referenced to dgnd v ih digital input high voltage l 2.0 v v il digital input low voltage l 0.8 v v oh digital output high voltage sourcing 500a l v + ? 0.3 v v ol digital output low voltage sinking 500a l 0.3 v digital input leakage v + = 5v, v ? = ?5v, v in = 0v to 5v l 2 a timing, v + = 2.7v to 4.5v, v ? = 0v (note 7) t 1 d in valid to clk setup l 60 ns t 2 d in valid to clk hold l 0 ns t 3 clk low l 100 ns t 4 clk high l 100 ns t 5 cs /ld pulse width l 60 ns t 6 lsb clk to cs /ld l 60 ns t 7 cs /ld low to clk l 30 ns t 8 d out output delay c l = 15pf l 125 ns t 9 clk low to cs /ld low l 0 ns downloaded from: http:///
ltc6915 6 6915fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: these parameters are tested at 5v supply; at 3v and 5v supplies they are guaranteed by design.note 3: these parameters are guaranteed by design. thermocouple effects preclude measurement of these voltage levels in high speed automatic test systems. v os is measured to a limit set by test equipment capability. note 4: if the total source resistance is less than 10k, no dc errors result from the input bias current or mismatch of the input bias currents or the mismatch of the resistances connected to in ? and in + . note 5: the psrr measurement accuracy depends on the proximity of the power supply bypass capacitor to the device under test. because of this, the psrr is 100% tested to relaxed limits at final test. however, their values are guaranteed by design to meet the data sheet limits. note 6: supply current is dependent on the clock frequency. a higher clock frequency results in higher supply current. note 7: guaranteed by design, not subject to test. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. timing, v + = 4.5v to 5.5v, v ? = 0v (note 7) t 1 d in valid to clk setup l 30 ns t 2 d in valid to clk hold l 0 ns t 3 clk low l 50 ns t 4 clk high l 50 ns t 5 cs /ld pulse width l 40 ns t 6 lsb clk to cs /ld l 40 ns t 7 cs /ld low to clk l 20 ns t 8 d out output delay c l = 15pf l 85 ns t 9 clk low to cs /ld low l 0 ns timing, dual 4.5v to 5.5v supplies (note 7) t 1 d in valid to clk setup l 30 ns t 2 d in valid to clk hold l 0 ns t 3 clk high l 50 ns t 4 clk low l 50 ns t 5 cs /ld pulse width l 40 ns t 6 lsb clk to cs /ld l 40 ns t 7 cs /ld low to clk l 20 ns t 8 d out output delay c l = 15pf l 85 ns t 9 clk low to cs /ld low l 0 ns downloaded from: http:///
ltc6915 7 6915fb typical performance characteristics input offset voltage vs input common mode input offset voltage vs input common mode input offset voltage vs input common mode error due to input r s vs input common mode error due to input r s vs input common mode error due to input r s vs input common mode input offset voltage vs input common mode input offset voltage vs input common mode input offset voltage vs input common mode input common mode voltage (v) 0 0.5 input offset voltage (v) 1.0 2.0 1.5 2.5 3.0 6915 g01 0 ?2 ?4 ?6 ?8 ?10?12 ?14 ?16 a v = 4096 a v = 256 a v = 16 a v = 1 v s = 3v v ref = 0.2v t a = 25c input common mode voltage (v) 20 ?2 ?4 ?6 ?8 ?10 ?12?14 ?16 ?18 input offset voltage (v) 6915 g02 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 a v = 4096 a v = 256 a v = 16 a v = 1 v s = 5v v ref = 0.2v t a = 25c input common mode voltage (v) ?5 input offset voltage (v) 8 64 2 0 ?2 ?4 ?6 ?8 ?10?12 ?14 3 6915 g03 ?3 ?1 1 5 ?4 4 ?2 0 2 a v = 4096 a v = 256 a v = 16 a v = 1 v s = 5v v ref = 0v t a = 25c input common mode voltage (v) 0 0.5 input offset voltage (v) 1.0 2.0 1.5 2.5 3.0 6915 g04 20 1510 50 ?5 ?10 ?15 ?20 v s = 3v v ref = 0.2v a v = 16 t a = 125c t a = 85c t a = 70c t a = ?50c t a = 25c input offset voltage (v) 20 1510 50 ?5 ?10 ?15 ?20 input common mode voltage (v) 1 4 0 6915 g05 2 3 5 v s = 5v v ref = 0.2v a v = 16 t a = 125c t a = 85c t a = 70c t a = ?50c t a = 25c 20 1510 50 ?5 ?10 ?15 ?20 ?25 input common mode voltage (v) ?5 input offset voltage (v) ?1 3 5 6915 g06 ?3 1 v s = 5v v ref = 0v a v = 16 t a = 125c t a = 85c t a = 70c t a = ?50c t a = 25c input common mode voltage (v) 0 additional offset (v) 10 0 ?10?20 ?30 ?40 ?50 0.5 1.0 1.5 2.0 6915 g07 2.5 3.0 v s = 3v v ref = 0.2v r + = r ? = r s c in < 100pf a v = 16 t a = 25c r s = 5k r s = 10k r s = 20k + ? r s r s c in r s = 15k input common mode voltage (v) 0 additional offset (v) 0 10 4 6915 g08 ?10?20 1 2 3 5 20 v s = 5v v ref = 0.2v r + = r ? = r s c in < 100pf a v = 16 t a = 25c + ? r s r s c in r s = 15k r s = 5k r s = 20k r s = 10k input common mode voltage (v) ?5 additional offset (v) 0 10 3 6915 g09 ?10?20 ?3 ?1 1 5 20 r s = 15k r s = 5k r s = 20k v s = 5v v ref = 0v r + = r ? = r s c in < 100pf a v = 16 t a = 25c + ? r s r s c in r s = 10k downloaded from: http:///
ltc6915 8 6915fb typical performance characteristics offset voltage vs temperature v os vs ref (pin 13) v os vs ref (pin 13) gain nonlinearity at gain = 1 (gain nonlinearity decreases for gain > 1) supply current vs supply voltage cmrr vs frequency error due to input r s mismatch vs input common mode error due to input r s mismatch vs input common mode error due to input r s mismatch vs input common mode input common mode voltage (v) 0 0.5 additional offset (v) 1.0 2.0 1.5 2.5 3.0 6915 g10 80 6040 20 0 ?20 ?40 ?60 ?80 v s = 3v v ref = 0.2v c in < 100pf a v = 16 t a = 25c + ? r + r ? c in r + = 0k, r ? = 20k r + = 20k, r ? = 0k r + = 0k, r ? = 15k r + = 15k, r ? = 0k input common mode voltage (v) 0 additional offset (v) 40 3020 10 0 ?10 ?20 ?30 ?40 4.0 6915 g11 1.0 0.5 1.5 2.5 3.5 4.5 2.0 3.0 5.0 + ? r + r ? c in r + = 20k, r ? = 0k v s = 5v v ref = 0.2v c in < 100pf a v = 16 t a = 25c r + = 0k, r ? = 20k r + = 15k, r ? = 0k r + = 0k, r ? = 15k input common mode voltage (v) ?5 ?4 ?2 0 2 4 additional offset (v) 30 2010 0 ?10?20 ?30 ?3 ?1 1 3 6915 g12 5 + ? r + r ? c in r + = 20k, r ? = 0k v s = 5v v ref = 0v c in < 100pf a v = 16 t a = 25c r + = 0k, r ? = 20k r + = 0k, r ? = 15k r + = 15k, r ? = 0k temperature (c) ?50 input offset voltage (v) 15 10 50 ?5 ?10 0 50 75 6915 g13 ?25 25 100 125 v s = 5v v s = 5v v s = 3v v ref (v) 0 v os (v) 4.0 6915 g14 1.0 2.0 3.0 2 ?3?8 ?13?18 0.5 1.5 2.5 3.5 v in + = v in ? = ref a v = 16 t a = 25c v s = 3v v s = 5v v ref (v) 0 1 3 5 7 9 v os (v) 20 10 0 ?10?20 ?30 ?40 2 4 6 8 6915 g15 10 v in + = v in ? = ref a v = 16 t a = 25c v s = 10v output voltage (v) ?2.4 gain nonlinearity (ppm) 5 43 2 1 0 ?1 ?2 ?3 ?4 ?5 ?1.2 0 0.6 6915 g16 ?1.8 ?0.6 1.2 1.8 2.4 v s = 2.5v v cm = v ref = 0v r l = 10k a v = 1 t a = 25c supply voltage (v) 2.5 supply current (ma) 8.5 1.15 1.101.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 6915 g17 3.5 11.5 4.5 5.5 6.5 7.5 9.5 10.5 t a = ?50c t a = 125c t a = 85c t a = 0c frequency (hz) 1 cmrr (db) 130 120110 100 9080 70 10 100 1000 6915 g18 v s = 3v, 5v, 5v v in = 1v p-p r + = r ? = 1k r + = r ? = 10k r + = 10k, r ? = 0k + ? r + r ? r + = 0k, r ? = 10k downloaded from: http:///
ltc6915 9 6915fb typical performance characteristics output voltage swing vs output current output voltage swing vs output current low gain settling time vs settling accuracy settling time vs gain internal clock frequency vs supply voltage additional gain error vs load resistance input voltage noise density vs frequency input referred noise in 10hz bandwidth input referred noise in 10hz bandwidth frequency (hz) 1 input referred noise density (nv/ hz ) 300 250200 150 100 50 0 10 100 1000 10000 6915 g19 a v = 16 t a = 25c v s = 5v v s = 5v v s = 3v time (s) 0 input reffered noise voltage (v) 3 21 0 ?1 ?2 ?3 2 4 6 8 6915 g20 10 v s = 3v t a = 25c time (s) 0 input reffered noise voltage (v) 3 21 0 ?1 ?2 ?3 2 4 6 8 6915 g21 10 v s = 5v t a = 25c output current (ma) 0.01 output voltage swing (v) 0.1 1 10 6915 g22 5.0 4.54.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = 25c v s = 5v, sourcing v s = 3v, sourcing v s = 5v, sinking v s = 3v, sinking sourcing sinking output current (ma) 0.01 output voltage swing (v) 0.1 1 10 6915 g23 5 43 2 1 0 ?1 ?2 ?3 ?4 ?5 v s = 5v t a = 25c settling accuracy (%) 0.0001 settling time (ms) 6915 g24 0.001 0.01 0.1 8 76 5 4 3 2 1 0 v s = 5v dv out = 1v g 100t a = 25c gain (v/v) 1 settling time (ms) 35 3025 20 15 10 50 10 100 1000 10000 6915 g25 v s = 5v dv out = 1v 0.1% accuracyt a = 25c supply voltage (v) 2.5 clock frequency (khz) 10.5 6915 g26 4.5 6.5 8.5 3.40 3.353.30 3.25 3.20 3.15 3.10 t a = ?55c t a = 85c t a = 125c t a = 25c load resistance r l (k) 0 additional gain error (%) 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 8 6915 g27 2 4 6 10 a v = 4096 a v = 256 a v = 16 downloaded from: http:///
ltc6915 10 6915fb pin functions in ? (pin 1/pin 2): inverting analog input. shdn (pin 1 gn package only): shutdown pin. the ic is shut down when shdn is tied to v + . an internal current source pulls this pin to v ? when floating. in + (pin 2/pin 3): noninverting analog input. v ? (pin 3/pin 4): negative supply. cs (d0) (pin 4/pin 6): ttl level input. when in serial control mode, this pin is the chip select input (active low); in parallel control mode, this pin is the lsb of the parallel gain control code. d in (d1) (pin 5/pin 7): ttl level input. when in serial control mode, this pin is the serial input data; in paral - lel mode, this pin is the second lsb of the parallel gain control code. hold_ thru (pin 5 gn package only): ttl level input for parallel control mode. when hold_ thru is high, the parallel data is latched in an internal d-latch.clk(d2) (pin 6/pin 8): ttl level input. when in serial control mode, this pin is the clock of the serial interface; in parallel mode, this pin is the third lsb of the parallel gain control code. d out (d3) (pin 7/pin 9): ttl level input. when in serial control mode, this pin is the output of the serial data; in parallel mode, this pin is the msb of the 4-bit parallel gain control code. in parallel mode operation, if the data in to d out (pin 9) is from a voltage source greater than v + (pin?12), then connect a resistor between the voltage source and d out to limit the current into pin 9 to 5ma or less. dgnd (pin 8/pin 10): digital ground. parallel_ serial (pin 9/pin 11): interface selection input. when tied to v + , the interface is in parallel mode, i.e., the pga gain is defined by the parallel codes (d3 ~ d0), i.e., cs (d0), data(d1), clk(d2), and d out (d3). when parallel_ serial pin is tied to v C , the pga gain is set by the serial interface. ref (pin 10/pin 13): voltage reference for pga output. out (pin 11/pin 15): amplifier output. the typical current sourcing/sinking of the out pin is 1ma. for minimum gain error, the load resistance should be 1k or greater (refer to the output voltage swing vs output current and gain error vs load resistance in the typical performance characteristics section). v + (pin 12/pin 16): positive supply. sense (pin 14 gn package only): sense pin. when the pga drives a low resistance load and the interconnect resistance between the out pin and the load is not neg - ligible, tying the sense pin as close as possible to the load can improve the gain accuracy. (dfn/gn) downloaded from: http:///
ltc6915 11 6915fb block diagrams (gn package only) (dfn package only) C + resistor array mux 4-bit latch q0 q1 q2 q3 q4 q5 q6 q7 8-bit shift-register hold_thru cs(d0) d in (d1) clk(d2) d out (d3) parallel_serial in C in + 32 11 67 8 9 c s c h v + v C shdndgnd 135 1610 14 out ref 15 14 c f 6915 bd01 sense gain control C + resistor array mux 4-bit latch q0 q1 q2 q3 q4 q5 q6 q7 8-bit shift-register cs(d0) d in (d1) clk(d2) d out (d3) parallel_serial in C in + 21 9 4 5 6 7 c s c h v + v C dgnd dgnd 10 128 3 out ref 11 c f 6915 bd02 gain control downloaded from: http:///
ltc6915 12 6915fb operation timing diagram d3 d3 d2 d1 d0 d7 ? ? ? ? d4 d3 d3 d4 d2 d1 d0 d7 ? ? ? ? d4 t 6 t 9 t 7 t 3 t 5 t 4 t 1 t 8 t 2 previous byte current byte clk d in cs/ld d out 6915 td theory of operation (refer to block diagrams) the ltc6915 uses an internal capacitor (c s ) to sample a differential input signal riding on a dc common mode voltage (the sampling rate is 3khz and the input switch- on resistance is 1k to 2k, depending on the power supply voltage). this capacitors charge is transferred to a sec - ond internal hold capacitor (c h ) translating the common mode voltage of the input differential signal to that of ref pin. the resulting signal is amplified by a zero-drift op amp in the noninverting configuration. gain control within the amplifier occurs by switching resistors from a matched resistor array. the ltc6915 has 14 levels of gain, controlled by the parallel or serial interface. a feedback capacitor c f helps to reduce the switching noise. due to the input sampling, an ltc6915 may produce aliasing errors for input signals greater than 1.5khz (one half the 3khz sampling frequency). however, if the input signal is bandlimited to less than 1.5khz then an ltc6915 is useful as instrumentation or as a differential to single-ended ac amplifier with programmable gain. parallel interface as shown in figure 1, connecting parallel_ serial to v + allows the gain control code to be set through the parallel lines (d3, d2, d1, d0). when hold_ thru is low (referenced to dgnd) or floating, the parallel gain control bits (d3 ~ d0) directly control the pga gain. when hold_ thru is high, the parallel gain control bits are read into and held by a 4-bit latch. any change at d3 ~ d0 will not affect the pga gain when hold_ thru is high. note that the dfn12 package does not have the hold_ thru pin. instead, it is tied to dgnd internally. the d out (d3) pin is bidirectional (output in serial mode, input in parallel mode). in parallel mode, the voltage at d out (d3) cannot exceed v + ; otherwise, large currents can be injected to v + through the parasitic diode (see figure 2). connecting a 10k resistor at the d out (d3) pin if parallel mode is selected (see figure 1) is recommended for current limiting.serial interface connecting parallel_ serial to v C allows the gain control code to be set through the serial interface. when cs is low, the serial data on d in is shifted into an 8-bit shift-register on the rising edge of the clock, with the msb transferred first (see figure 3). serial data on d out is shifted out on the clocks falling edge. a high cs will load the 4 lsbs of the shift-register into a 4-bit d-latch, which are the gain control bits. the clock is disabled internally when cs is pulled high. note: clk must be low before cs is pulled low to avoid an extra internal clock pulse. downloaded from: http:///
ltc6915 13 6915fb operation d out is always active in serial mode (never tri-stated). this simplifies the daisy chaining of the multiple devices. d out cannot be wire-or to other spi outputs. in addition, d out does not return to zero at the end of transmission, i.e. when cs is pulled high. a ltc6915 may be daisy-chained with other ltc6915s or other devices having serial interfaces by connecting the d out to the d in of the next chip while clk and cs remain common to all chips in the daisy chain. the serial data is clocked to all the chips then the cs signal is pulled high to update all of them simultaneously. figure 4 shows an example of two ltc6915s in a daisy chained spi configuration. figure 1. pga in the parallel control mode figure 2. bidirectional nature of d out /d3 pin figure 3. diagram of serial interface (msb first out) 4-bit gain control code 4-bit latch q0 q1 q2 q3 q4 q5 q6 q7 8-bit shift-register d out (d3) clk d in cs 6915 f03 v C v + dgnd d out (d3) 6915 f02 (internal node) shdnin C in + v C hold_thrucs(d0) d in (d1) clk(d2) v + out sense ref nc p/s dgnd d out (d3) ltc6915 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 v out v in 0.1f parallel gain control code = 1010 v out = 2 9 v in = 512v in shdnin C in + v C hold_thrucs(d0) d in (d1) clk(d2) v + out sense ref nc p/s dgnd d out (d3) ltc6915 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 v out v in 0.1f gain is set by microprocessor. a 10k resistor on d out (d3) protect the device when v d3 > v + p 5v 5v d0d1 d2 d3 10k 6915 f01 downloaded from: http:///
ltc6915 14 6915fb operation figure 4. 2 pgas in a daisy chain the amplifiers gain is set as follows: d3, d2, d1, d0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101~ 1111 gain 0 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 input voltage range the input common mode voltage range of the ltc6915 is rail-to-rail. however, the following equation limits the size of the differential input voltage: v C (v in + C v in C ) + v ref v + C 1.3 where v in + and v in C are the voltage of the differential input pins, v + and v C are the positive and negative sup - ply voltages respectively and v ref is the voltage of ref pin. in addition, v in + and v in C must not exceed the power supply voltages, i.e., v C < v in + < v + and v C < v in C < v + 5 volt operation when using the ltc6915 with supplies over 5.5v, care must be taken to limit the maximum difference between any of the input pins (in + or in C ) and the ref pin to 5.5v, i.e., |v in + C v ref | < 5.5 and |v in C C v ref | < 5.5 if not, the device will be damaged. for example, if rail-to-rail input operation is desired when the supplies are at 5v, the ref pin should be 0, 0.5v. as a second example, if the v + pin is 10v, and the v C and ref pins are at 0, the inputs should not exceed 5.5v. shdnin C in + v C hold_thrucs(d0) d in (d1) clk(d2) v + out sense ref nc p/s dgnd d out (d3) ltc6915 #2 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 v out d out v in 0.1f shdnin C in + v C hold_thrucs(d0) d in (d1) clk(d2) v + out sense ref nc p/s dgnd d out (d3) ltc6915 #1 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 v out v in 0.1f 0.1f 0.1f 0.1f p C5v C5v C5v 0.1f C5v 6915 f04 cs d in clk clk d in cs/ld d15 d11 d10 d9 d8 d7 d3 d2 d1 d0 gain code for #2 gain code for #1 downloaded from: http:///
ltc6915 15 6915fb operation settling time the sampling rate is 3khz and the input sampling period during which c s is charged to the input differential voltage, v in , is approximately 150s. first assume that on each input sampling period, c s is charged fully to v in . since c s = c h (= 1000pf), a change in the input will settle to n bits of accuracy at the op amp noninverting input after n clock cycles or 333s(n). the settling time at the out pin is also affected by the internal op amp. since the gain bandwidth of the internal op amp is typically 200khz, the settling time is dominated by the switched-capacitor front end for gains below 100 (see the low gain settling time vs settling accuracy and the settling time vs gain graphs in the typical performance characteristics section). in ad - dition, the worst case settling time after a device-enable (active low on pin 1 of a gn package) is equal to the settling due to the gain plus the input settling time (333s ? n). for example, if an ltc6915 is enabled with a logic high on pin 1 then, the maximum settling time to 10 bits of ac - curacy (0.1%) and a gain equal to 100 is 8.33ms ([333s ? 1024] + 5ms). input current whenever the differential input v in changes, c h must be charged up to the new input voltage via c s . this results in an input charging current during each input sampling period. eventually, c h and c s will reach v in and ideally, the input current would go to zero for dc inputs. in reality, there are additional parasitic capacitors which disturb the charge on c s every cycle even if v in is a dc voltage. for example, the parasitic bottom plate capacitor on c s must be charged from the voltage on the ref pin to the voltage on the in C pin every cycle. the resulting input charging current decays exponentially during each input sampling period with a time constant equal to r s c s . if the voltage disturbance due to these currents settles before the end of the sampling period, there will be no errors due to source resistance or the source resistance mismatch between in + and in C . with r s less than 10k, no dc errors occur due to input current mismatch. in the typical performance characteristics section of this data sheet, there are curves showing the additional error from non-zero source resistance in the inputs. if there are no large capacitors across the inputs, the amplifier is less sensitive to source resistance and source resistance mismatch. when large capacitors are placed across the inputs, the input charging currents are placed across the inputs. the input charging currents described above result in larger dc errors, especially with source resistor mismatches. power supply bypassing in a dual supply operation, connect a 0.1f bypass ca - pacitor from each power supply pin (v + and v C ) to an analog round plance surrounding an ltc6915. the bypass capacitor trace to the supply pins must be less than 0.2 inches (an x7r or x5r capacitor type is recommended). in single supply operation, connect the v C pin to the analog ground plane and bypass the v + pin. shutdown modesthe ic has two shutdown modes, hardware shutdown and software shutdown. when shdn is tied to v + , the ic is in hardware shutdown mode. during this shutdown mode, the gain setting digital interface (serial or parallel) and the main op amp are both disabled, thus the pga dissipates very small supply current (see the electrical characteristic table). when shdn is floating, an internal current source will pull it down to v C . the digital interface is turned on to read the gain setting codes. the ic is in normal amplifica - tion mode as long as the gain control code is other than 0000. if the gain control code is 0000, the ic operates in software shutdown mode, i.e., the main op amp is turned off so that the pga dissipates less power. the dfn package does not have hardware shutdown. setting the voltage at the ref pin the current coming out of the ref pin may affect the reference voltage at the ref pin (v ref ). if v ref is set by a resistive divider then the v ref voltage is a function of the v out voltage (see figure 5). in order to minimize the v ref variations, the total resistance of r1 plus r2 should be much less than 32k (5k or less) or use a voltage refer - ence to set v ref . figure 5 C + ref i ref = v out C v ref 32k v out v + v C r1r2 ltc6915 r = 32k 6915 f05 v v r v k v r rr k re f out =+ + ?? ?? ?? ?? + 12 12 32 32 ? ?( ) v ref 0.1f out downloaded from: http:///
ltc6915 16 6915fb package description typical application figure 6. a 2:1 multiplexing two ltc6915?s with daisy chained gain control multiplexing two ltc6915?s send a gain code of 0000 to one ic to set its output to a high impedance state and send a gain code other than 0000 to the second ic to set it for normal amplification. if both devices are on, the 200 resistors protect the outputs. the sense pin connection maintains gain accuracy for loads 1k or greater. shdnin C in + v C hold_thrucs d in clk v + out sense ref nc par_ser dgnd d out ltc6915 #1 C5v C5v p (ttl levels) data select clock 0.1f 0.1f 5v v in1 shdnin C in + v C hold_thrucs d in clk v + out sense ref nc par_ser dgnd d out ltc6915 #2 C5v C5v 0.1f 0.1f 5v v in2 v out 200 200 6915 f06 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note:1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notchr = 0.20 or 0.35 45 chamfer pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (ue12/de12) dfn 0806 rev d 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 3.30 0.10 0.25 0.05 0.50 bsc 1.70 0.05 3.30 0.05 0.50 bsc 0.25 0.05 gn16 (ssop) 0204 1 2 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note:1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695 rev d) gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) downloaded from: http:///
ltc6915 17 6915fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 6/11 revised units for psrr in electrical characteristics 5 (revision history begins at rev b) downloaded from: http:///
ltc6915 18 6915fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0611 rev b ? printed in usa related parts typical application shdnin C in + v C hold_thrucs(d0) d in (d1) clk(d2) 12 3 4 5 6 7 8 23 4 5 sdo sck cs fo 89 7 10 ref + ref C in + in C 1615 14 13 12 11 10 9 v + out sense ref nc par_ser dgnd d out (d3) ltc6915 c5 0.1f c2 0.1f c1 0.1f 0v measure standby v + v + v + v + v + control signal 10k 1615 14 13 12 28 v ss v ss 8 19 bridgesensor r < 10k 20 10k lt1790-1.25 v in v out gnd1 gnd2 c3 0.1f c3 1f zetekzxm61p02f 6 4 1 2 v cc gnd ltc2431 mosimiso sclk cs1 cs2 rc5/sdo rc4/sdi/sda rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 rb7 ras/an4/ss ra4/t0clk1 v dd pic16lf73 1.25v 6915 f07 6 1 76 x14mhz 9 10 1 v + osc1/clkin osc2/ clkout mclr/ v pp part number description comments ltc1043 dual precision instrumentation switched-capacitor building block rail-to-rail input, 120db cmrr ltc1100 precision zero-drift instrumentation amplifier fixed gains of 10 or 100, 10v offset, 50pa input bias current ltc1101 precision, micropower, single supply instrumentation amplifier fixed gain of 10 or 100, i s < 105a ltc1167 single resistor gain programmable, precision instrumentation amplifier single gains set resistor, g = 1 to 10,000 low noise: 7.5nv/ hz ltc1168 low power single resistor gain programmable, precision instrumentation amplifiers i s = 530a ltc1789-1 single supply, rail-to-rail output, micropower instrumentation amplifier i s = 80a max ltc2050 zero-drift operational amplifier sot-23 package ltc2051 dual zero-drift operational amplifier ms8 package ltc2052 quad zero-drift operational amplifier gn16 package ltc2053 rail-to-rail input and output, zero-drift instrumentation amplifier with resistor-programmable gain ms8 package, 10v max v os , 50nv/c max drift ltc6800 rail-to-rail input and output, instrumentation amplifier with resistor-programmable gain ms8 package, 100v max v os , 250nv/c max drift figure 7. bridge amplifier with programmable gain and analog to digital conversion. (standby current less than 100a) downloaded from: http:///

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